半加法器

module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

9/28 程式碼

Behavioral Verilog

module top 3
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a&b;
endmodule

module system_clock(clk);
parameter PER10D=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PER10D/2)clk=~clk;
#(PER10D-PER10D/2)clk=~clk;
end
always @(posedgc clk)
if($time>1000)#(PER10D-1)$STOP;
endmodule